The present invention relates to a technique effective in its application to a packaging technique in a method for manufacturing a semiconductor integrated circuit device (or a semiconductor device).
In Japanese Unexamined Patent Publication No. 2007-214237 (Patent Literature 1) there is disclosed a technique wherein, in a packaging process for a resin-sealed package with less external leads like, for example, a discrete transistor, resin burrs on the leads are removed by a simple burr discriminating method using a laser and a water jet, followed by solder plating.
In Japanese Unexamined Patent Publication No. 2001-102510 (Patent Literature 2) there is disclosed a technique wherein, in a packaging process for a resin-sealed package such as an IC package, tie bars are cut after resin sealing and resin burrs remaining between leads are removed using a CO2 laser, followed by solder plating.
In Japanese Unexamined Patent Publication No. 2000-299400 (Patent Literature 3) there is disclosed a technique wherein, in connection with a non-leaded flat package, a sealing material present between leads is removed by a punching die and exposed leads are covered with metal coating by plating for enhancing the solder adherability, in order to prevent a short-circuit between leads at the time of packaging.    [Patent Literature 1]    Japanese Unexamined Patent Publication No. 2007-214237    [Patent Literature 2]    Japanese Unexamined Patent Publication No. 2001-102510    [Patent Literature 3]    Japanese Unexamined Patent Publication No. 2000-299400